Release notes

Footprint source Package for PE-BOM-010

SnapEDA / Ultra Librarian footprints stamp ``Package`` (e.g. ``TDFN-8 Maxim``) and ``SnapEDA_Link`` on the ``.kicad_mod`` or embedded ``.kicad_pcb`` footprint. BoardLab now parses that source document metadata into ``cad_footprints`` and prefers the vendor Package label when classifying land family for PE-BOM-010 — not only the IPC-style Lib:Name (``SON50P…``).

Library registers CAD footprints

After graph build, each IC’s KiCad ``Lib:Name`` is stored on the extract as ``cad_footprints`` (project + shared library). When the ``.kicad_mod`` resolves, ``descr`` / ``tags`` are parsed from that footprint source file so PE-BOM-010 classifies land family from real CAD metadata, not only the name string.

TDFN-EP ≡ SON for PE-BOM-010

Emmaforo U5 MAX17048: datasheet ``TDFN-EP`` vs KiCad ``SON50P200X200X80-9N`` was a false PE-BOM-010 ERROR. Same no-lead EP land family (Maxim TDFN / IPC SON).

Resume extracts newly added ICs

``mode=failed`` / resume skipped the whole ``ic_extraction`` stage when *any* ``extracted/*.json`` already existed. Adding MAX17048 (U5) after U1–U4 were extracted left schema reviewable from PDF but no pintable JSON — PCB AI then skipped U5 as “no library extraction”.

Overview run bar tracks PCB stages

The bottom RunStatusBar on Overview treated PCB SSE stage ``checks`` as unknown (``pcb_checks``), so the bar stayed near 0% through deterministic checks / AF and only jumped late in AI review.

Find Maxim datasheets (MAX17048G_T10)

Auto-download tries harder before asking for an upload: schematic ``MAX17048G_T10`` (underscore tape-reel) now also searches ``MAX17048G+T10`` / ``MAX17048G`` / ``MAX17048``, and Analog/Maxim PDF URLs are candidates. Misses still surface as not-reviewed + upload.

Extract die bonds + pull-up/down

Pintable extraction must scan the block diagram and pin notes for ``internal_features``: ``connected_pin_groups`` (die shorts), ``pullup_pins`` / ``pulldown_pins`` (external pulls required). Empty lists when the PDF is silent — never invent. PE-INT-002 warns when a listed pull-down has no resistor to ground.

Internal pin bonds (VIN↔VINA)

Datasheet die shorts belong in ``internal_features.connected_pin_groups``. ``shortest_path`` reports them; PE-REV no-path rows that contradict a bond are dropped. Emmaforo TPS63031: VINA/EN/PS on a bypass star with VIN on VSYS matches the typical application — VIN↔VINA is on-die, not a board error.

SON/WSON ≡ TI DSK (not QFN)

PE-BOM-010 treated TI ``SON (DSK)`` extracts that mention ``QFN-10 (… R-PWSON-N10)`` as QFN, so a correct KiCad ``Package_SON:WSON-*`` looked like a family mismatch (Emmaforo U4 TPS63031DSKR). WSON/USON/PWSON/VSON canonize to SON; when both QFN and SON codes appear, SON wins. Bare QFN vs WSON still ERROR.

KiCad ``(mirror x/y)`` axis semantics

KiCad ``(mirror x)`` reflects across the X axis (negates Y); ``(mirror y)`` reflects across the Y axis (negates X). BoardLab had the axes swapped, so Emmaforo J3 (``mirror x``) pin tips landed on the wrong side of the symbol: pin 1 missed the BAT wire/label and pin 2 missed the power:GND flag.

NetIndex: first-class net identity

Introduce ``NetCluster`` / ``NetIndex``: electrical identity is the ``{(ref, pin)}`` member set; KiCad strings are aliases. PE-LAY and PE-NC consume the index instead of comparing display names ad hoc.

PE-LAY by pad-set membership (not name shape)

Replace the anonymous-name PE-LAY shortcut with electrical identity: sch and PCB nets match when their ``{(ref, pin)}`` sets are equal, even if KiCad display strings differ. PE-NC-001 warns only when other parts share the net (floating NC is correct). Keeps 2.87.119 KiCad same-text merge for power + local labels.

Sch net merge: power + local same text

KiCad joins a power symbol and a local label with the same text into one net; BoardLab bucketed them by label kind and invented a second name via collision rename (``VSYS`` → ``VSYS_``).

KiCad sch pin Y flip (symbol editor → sheet)

``.kicad_sch`` ``lib_symbols`` pin coordinates use symbol-editor axes (Y up). Schematic sheets use Y down. Pin placement now negates Y before rotate/mirror so tips land on the wires KiCad draws. Without this, power pins on modules such as ESP32-C6 looked swapped (GND↔3V3) and schema/PCB conformity falsely failed on a correct board (Emmaforo).

Library rescan first; real admin names

Idle library realignment runs on the asyncio lifespan loop (not a daemon thread that can stall under uvicorn), ticks every 15s while a stale/missing-power backlog remains, and keeps popular ingest paused until rescan clears. Admin Users / Projects / Usage show the local account display name (e.g. Michele Bigi), not the raw ``usr_…`` id.

Charger IIN is not a VBUS load

BQ25896-class path ICs were counted as VBUS peak loads when the KiCad symbol pin numbers disagreed with the datasheet pintable (pin 1 = VBUS in the PDF but GND on the board). IIN / adapter current limit (3.25 A) must not become ``i_peak_a`` next to I(VBUS) IQ — it is path capacity.

iPadOS navigation chrome

Menus and project tabs move to an iPad-style split view: persistent sidebar (264px, frosted, 44px rows, blue selected tint), content-pane top bar for utilities only, segmented control for sibling panels (Parts|Derating, Rails|Domains|Impedance, Project|Fabrication), and a compact bottom tab bar with a left sheet. Admin Library is a flat sidebar group (no accordion).

Hierarchical .kicad_sch care

BOM-from-schematic and netlist walk every KiCad ``Sheetfile`` child, including nested subdirectories (``power/rails.kicad_sch`` → ``ldo.kicad_sch``). Companion sheets stored under ``uploads/`` keep relative paths. Clearer error when a Sheetfile child is missing; bom_parse logs sheet count.

Netlist from schematic (not PCB copper)

Schematic connectivity is the design IR. A present ``.kicad_pcb`` no longer replaces nets or invents PCB-only footprints (e.g. U3 on copper but missing from the sheet). Pad nets are a fallback only when the schematic yields zero nets. Layout checks still use ``layout_graph`` separately.

BOM from schematic (KiCad)

For KiCad projects the schematic is the BOM source of truth. Each schema run regenerates ``bom.csv`` from symbol fields (hierarchical sheets included). IC ``Value`` fills MPN when the manufacturer field is empty. PCB-only footprints are not invented into the BOM.

Schema progress bar after prepare

Starting schematic analysis right after prepare no longer loses the bottom status bar. Heal used the stale ``pipeline_prepared`` event / graph-without- report to force ``ready`` while the schema worker was still queued — worker logged ``booted into non-queued`` and the UI showed no progress.

TVS IPP is not a rail load peak

Extract/library must not put Peak pulse current (IPP, 8/20 µs) into `power_requirements.i_peak_a`. That is abs-max clamp capability; rail budget uses leakage IR for ESD/TVS. Fixes EmmaForo2 VBUS false FAIL (4.5 A IPP vs 3.25 A adapter).

Story Bench polish

Legacy `?section=protocols|bom_coverage` URLs redirect to Interfaces / Coverage. Chapter empty states distinguish **—** from **Pass**. Bench nav keeps story order (1…8) for accessibility.

Story Bench lens Schema | PCB | Both

One project report with a lens toggle. **Both** merges schema + PCB findings (PCB wins on the same finding_id), prefers PCB rail budget and protocol cert, and recounts severity from the deduped list. Bare `/report` opens Both when both runs exist.

Buses chapter from bus-only reviews

PE-REV findings that are bus-only (I2C/SPI/I2S/…) route to the Buses chapter so it is no longer empty when pull-up/concordance issues exist. Mixed power+bus reviews stay in IC dossiers.

Power rail dossiers

Power / PDN opens one dossier per rail: budget (I_ord/I_peak/I_cap) plus linked findings grouped as decoupling, filter, copper/geometry, other.

IC dossiers structured by theme

IC dossiers chapter opens one panel per designator with themed buckets (Power, Buses, Interfaces, Thermal, Placement, …) instead of a flat list.

Story Bench panel metrics + headline

Each Story Bench panel shows 2–3 bench metrics (rails/MARGIN, IC count, fixtures certified). A one-line board headline sits above the map.

Story Bench report (A+B hybrid)

Report home is a **Story Bench**: board story order as test-bench panels. Power / PDN → Buses → Interfaces → SI/HF → Thermal → Protection → **IC dossiers** (IC-by-IC, PE-REV no longer dumped in Coverage) → Coverage. Markdown export follows the same chapters (severity is a filter, not the spine).

Module MPN must not bind SoC datasheet

HubAudio USB on ESP32-S31-WROOM-3 pads 40/41 was correct; the false warning came from binding the bare **ESP32-S31 Series** (QFN80) PDF to the WROOM module MPN. Module tokens (WROOM/WROVER/MODULE/SIP) must match on both sides of datasheet lookup and pintable `base_family`.

Serial buses match net name + IC pinout

I2C/SPI/I2S recognition requires net-name and pinout concordance (or one side only when the other is silent). SPI_* nets with dual-function SCL/SDA pins are not I2C; power/GND nets never carry serial roles.

Mandatory per-rail V + I extract (1.20.0)

Pintable extract must fill every IC supply domain: voltage, ordinary load, max load. Datasheets always state these in ROC / Electrical Characteristics — validation rejects omissions. Parser bump **1.20.0** drives library idle reparse.

Recognize SPI / I2C / I2S buses

Physical-bus recognition now builds `i2c-pcb` / `spi-pcb` / `i2s-pcb` instances from pin↔net connectivity (pin names and net names), then runs them through L0–L3 like USB/ETH. No invented ohms or MHz.

Finding quality: less WARNING spam

HubAudio PCB triage: identical PE-PLC-004 ×5, WARNING on missing evidence, RMII "not certified" + "certified" on the same PHY, phantom BUD rails.

DDR JEDEC VDD cites (no invented PCB Z)

Wire on-file JESD79 DDR1–5 into the protocol catalog for **DRAM VDD** only. PCB geometry (Z0 / skew-mm / length) stays CONTROLLER_DEPENDENT / PHY_DEPENDENT — JEDEC does not state a universal board impedance.

IC review BrokenPipe under concurrent PDF ingest

HubAudio 2.87.92/93 lost all 25 IC LLM reviews (`BrokenPipeError` turn 0) while a single `review_ic_async` still succeeded. Root cause: pipeline worker reused uvicorn→Docker stderr; concurrent datasheet ingest flooded that pipe with fontTools/pypdf warnings until writes raised EPIPE inside the review.

Stop PE-PRT multiplying on incremental report writes

HubAudio re-run showed PE-PRT-L1-002 still ×52 INFO: `_write_report` re-extended `protocol_exam` findings after every IC. Strip prior `protocol_l*` before extend; lock concurrent writes. Collapse-per-instance (2.87.91) was fine.

Same-cause WARNING aggregation

Warnings with the same root cause collapse to one card that lists every IC:

Schematic software FP cleanup

HubAudio schematic report noise (engine, not hardware):

Project tab BOM → Parts

Michele: flat tab row should say **Parts**, same as the table heading — not BOM. URL stays `?tab=bom` for compatibility.

SPI / QuadSPI protocol PDFs on file

Michele: Motorola SPI Block Guide + SPI family / QuadSPI sources. On-disk archive (gitignored):

JEDEC DDR1–5 specs on file

Michele pointed at [TheRamGuide-WIP-](https://github.com/RAMGuide/TheRamGuide-WIP-) for DDR protocol PDFs. On-disk archive (gitignored PDFs):

Fix IC review BrokenPipe / Event loop closed

HubAudio (and any exam) lost every IC LLM review with `BrokenPipeError` / `RuntimeError: Event loop is closed`. Root cause: `get_provider_by_name` is `lru_cache`d and `DeepSeekProvider` held one process-lifetime `AsyncOpenAI` httpx client. Idle library refresh / popular ingest call `asyncio.run()` in a background thread — each run opens sockets on a temporary loop, then closes that loop. The next review reused the cached client and died while closing sockets bound to the dead loop (turn 0, all ICs). Fix: provider stores credentials only; each session gets its own `AsyncOpenAI` and `session.close()` awaits `client.close()` on the live loop.

CI seed fix + optical S/PDIF ERROR stays

Michele: CI mail spam from Backend pytest; after PE-BUD cleanup S/PDIF must remain an **ERROR** (true positive), not vanish with the rail FPs.

Rail budget: pin roles + supply abs-max only

Michele: HubAudio PE-BUD ERROR were FP — fix root cause, not a suppress patch. ``I2S_IN_*`` / ``I2S_OUT_*`` net names no longer invent regulators (VIN/VOUT match is pin-token only). Load abs-max ignores sense/VIN/bus measurable current (INA228 85 A class); peak keys drop bare ``imax``/``i_abs``.

Project tabs: flat single row

Michele: not a multi-level sheet menu — **all tabs on one line**. Overview · BOM · Derating · Rails · Domains · Impedance · Project · Fabrication. No second-row schede. ``?tab=parts&panel=…`` from 2.87.83 still resolves.

Project workspace: section + panel (superseded)

Two-level chrome (section row + panel schede). Superseded by 2.87.84 flat row; resolver kept for old URLs.

Global pin-sort fix (KiCad sch is enough)

Michele: create-project 500 on mixed pin numbers (USB-C ``1`` + ``A5`` / ``EP``). **Global** fix in ``natural_sort_key`` — not a HubAudio-only patch. KiCad ``.kicad_sch`` (+ ``.kicad_pcb``) remains the required input; no separate PADS netlist. The API route is still named ``upload/netlist`` (legacy).

HDMI TMDS from TMDS1204 + Admin Mail compose/redirect

Michele: missing HDMI Adopter TMDS Z → take 90 Ω from the TI TMDS1204 component seed (VENDOR, UNOFFICIAL). Admin Mail: compose/send + contact redirect address override.

USB3/4 NUMERIC Z from on-file PDFs

Michele: pack board Zdiff numerics from the PDFs already on disk — never invent ohms.

Protocol PDF archive + missing-pack cites

Michele: where official PDFs are public, put them on disk; otherwise keep a usable vendor/helper PDF and mark the cert pack ``UNOFFICIAL``.

Integrate cert provenance (no false OFFICIAL)

Michele: continue Admin Certs / Library — integrate packs that already have cites on file; stop marking HDMI TMDS as OFFICIAL from CEC-only; helper bus packs (SGMII Cisco, RMII Micrel) show as UNOFFICIAL until a chip MPN links.

Admin Certs provenance + chip bus versions

Michele: separate packs missing an official document; one Admin list with a provenance field (official → unofficial → component bus). IC-dependent buses (RMII+) annotate versions by chip MPN so they are looked up again without re-downloading datasheets every time.

Admin menu reorg

Logical Admin IA: nested Library submenu, one Users surface, MySQL credentials visible to admins, batch processor queue list.

Test deploy

Quiet Studio UI primitives

UI controls use 8px radius, panels 11px, 150ms transitions.

Admin Mail inbox

Michele: Admin page to read contact mail; reuse the existing contact HTML template.

Completion alert in Settings

Michele: if the user opts in via Settings, email them when analysis finishes. Toggle lives in the top-bar Settings sheet (same pref as Account).

Email auth + completion alerts

Michele: while Stripe is set up, wire local email auth (forgot / reset / change password) and optional alerts when schema or PCB analysis finishes.

Stripe as free-to-start payments

Michele: use a free payment platform for credits. **Stripe** (Italy) has no monthly/setup fee — only per successful charge (~1.5% + €0.25 EEA cards). Already wired; `/credits` copy and `.env.example` point to signup. Without keys, manual pack requests + Admin Grant still work.

Credits metering + free-service flag

Michele: enable credits even before selling; Admin → Software → Users can turn **Free service** on per user; `/credits` page for balance and packs. Stripe optional (no monthly fee — only transaction fees); without keys, pack buttons create a manual payment request that admin fulfills with **Grant**.

Cert engine reads cert_library JSON packs

Michele: every certification's component/requirement specs live as JSON in `cert_library`; the certifying engine must grade from that SoT. `load_certifying_catalog()` overlays pack constraints onto the recognition skeleton; L0–L3 / CertifyingEngine / AF impedance cites use it.

Cert system: family labels + Admin Certs UX

Michele: certification is first-class. Fix broken pack bus labels (`1000base` from pack-id split), seed with USB/ETHERNET/HDMI families + human titles, dedupe document requests, Admin Certs grouped by family. Auto-refresh packs still on parser `< 1.1.0` at boot. Seed endpoint allowed for admins.

Cert packs auto-seed

Empty certification library was a config gap — BoardLab seeds protocol-catalog packs (USB / Ethernet / HDMI / …) on boot when `cert_library.sqlite` has zero rows. Admin → Software → Certs also has **Seed from protocol catalog**.

Menu decisions · PCBWay fab default

Michele menu decisions: Library only in Admin side nav (not top bar); Contact only inside a project; keep Overview|Schema|PCB; kill Exam; Parts tabular; Settings + PCBWay default from PCB layers; boardlab-* downloads; BoardLabMark.

Quiet Studio A+1 (chosen)

Michele chose IA **Studio** + look **Quiet Studio**. Guidelines locked in `docs/development/QUIET_STUDIO_UI.md`. Dark accent stays `#007AFF`; dashboard/report/admin chrome aligned.

Library tab restore · Apple Studio shell

Library is again an Admin Software tab (Overview | Jobs | Library | Certs | Users). Project default is **Overview** (run pulse), not the BOM table. BOM lives under Parts. Ops for exam runs extracted to `useProjectExamOps`.

Library archive · MySQL admin · JSON

Config · Library Archive tab: no giant in-app tables. Opens Adminer (`/library-db/`) for library MySQL; ZIP backup/download; JSON component archive export/import.

Config · Library (unified)

Top-nav Library opens **`/config/library`** with Catalog | Review | Autoscan. Admin Software no longer duplicates Library (legacy `?tab=library` redirects). Old `/library` redirects here.

Admin Software Library/Certs polish

Software Overview shows processes in progress; Library lists (components / scan / obsolete) stay behind expand buttons with export/import and autoscan start/stop; Certs adds document requests + explicit source.

Admin Software IA + remove onboarding survey

Admin left nav matches Software config instructions: **Overview | Jobs | Library | Certs | Users** as first-class Software items (not a nested bolted-on tab). Ops tools (Projects, Components, Credits, …) sit in a separate group. Onboarding survey no longer appears on first login / dashboard.

Admin Software config · idle autoscan · SMTP seam

Admin **Software** tab: overview (jobs, library, certs, users, autoscan, email) plus Jobs | Library | Certs | Users. Library autoscan is toggleable (persisted, default ON); idle datasheet RESCAN still has priority over popular ingest. SMTP env stubs (`SMTP_*` / `ADMIN_EMAIL`) with no-op `send_email` until credentials arrive.

Show Zdiff for differential PCB nets

ImpedenceFinder inventory table showed "—" on USB_D± because pair results live in ``zdiff_*``, not ``z0_*``. UI now shows Zdiff (avg / min–max) for differential nets and keeps Z0 for single-ended.

Scrub library MySQL secrets from compose

Remove default MySQL passwords / DSN from `docker-compose.yml`. Library MySQL credentials live only in `.env` (required vars). Healthcheck uses the image helper (no password in compose).

Library rescan priority · MySQL · bundle

Idle **datasheet rescan** (stale parser / missing power) runs before popular new-IC ingest. Component library runtime is **MySQL only** (compose `library-mysql`; SQLite only via explicit test constructor / `BOARDLAB_LIBRARY_ALLOW_SQLITE=1`). Admin Management tab: **download / upload** BoardLab library ZIP.

Library Management / Catalog tabs

Admin Library page splits the two jobs into top-level tabs: **Management** (LibraryAccess triage — parser/scan/power/review) and **Catalog** (browse ICs/passives/discrete/datasheets + PDF import). Same store; less stacked UI.

Library scan column + skills_manifest fix

BoardLab admin Library table shows **scan** version and a **review** checkbox when a row is stale, missing power, or idle-refresh pending. Restores valid `skills_manifest.json` (missing `{` broke default parser + LibraryAccess queries and idle ingest).

BoardLab landing rewrite

Public home is a new **BoardLab** page (navy / copper / teal, loupe mark, Fraunces + Source Sans). Instructions: create project → upload → exam; file needs + link to File guide. Logo pack from 2.87.37 kept.

Library tab admin-only

**BoardLab** Library management (catalog + LibraryAccess table) is visible and callable only for admins. Project exam still uses `/api/library/check` for all authenticated users. Logo/casing from 2.87.37 untouched.

BoardLab casing + loupe mark

User-facing product name is **BoardLab** (capital L in Lab). New mark: PCB board edge + lab loupe (navy / copper / teal). Domain stays `boardlab.it`.

CertifyingEngine E2–E5 (Grade · UI · class · tiers)

**BoardLab** cert engine completes S1: Detect→Instantiate (E1) plus Grade full, Present UI, class-check unify, and evidence-only tiers. Present-only cards; no board-name hardcoding.

BoardLab brand + boardlab.it dual-host

User-facing product brand is **BoardLab**; primary public URL **https://boardlab.it**.

Stack tip: rail capacity + board-map + metaphor + naming + E1

Board-map is the single report shell; metaphor A+B empty/bench copy folded in (no duplicate map). CertifyingEngine **E1** Detect→Instantiate for ETH/HDMI. No ETH recognize patch.

Board-agnostic rail source capacity

Michele: rail power budget must grade PASS/MARGIN/FAIL whenever capacity can be deduced from **library / datasheet / part class / net topology** — never leave USB / charger / LDO rails UNKNOWN for lack of a contact rating, and **never** special-case a project or board name.

Cert cards + HDMI/ETH under Certifications

Michele: HDMI and Ethernet must be visible under **Certifications**; each protocol gets a **card** (`USB-3.0 — certified` / `not certified`, blue/red) with requirements **OK** (green) / **NO** (red) and remediation. Hard rule: only protocols **present** on the board; nested lower rates (100BASE-TX under GbE, HDMI 1.4 under 2.0, USB2 under USB3) may PASS when the higher rate FAILs — never invent Gigabit on a 10/100-only PHY.

Auto-reparse stale component on examine

Michele: when examining a component whose library row is behind the current parser version, re-parse from the datasheet and KiCad footprint/symbol, upsert into the component library (writer-gated remotely), then continue the exam with fresh data. One MPN only — idle batch stays paused.

Rail power budget report card

Michele: dedicated **Rail power budget** card on the report (not only PE-BUD in the findings tree). Per-rail ordinary/peak vs source with PASS/MARGIN/FAIL/UNKNOWN colors, remediation when failing. PE-BUD now also runs in the **PCB** pipeline (was schematic-only for findings; PCB already used rail peak for PE-PWR/VIA).

Certifications together in findings tree

Michele: certification findings must live in **one** place in the report tree — not scattered under Error / Warning / Info. The tree keeps severity folders for non-protocol findings, then a single top-level **Certifications → Protocols** branch with every protocol instance and PE-PRT finding. Existing severity and PASS-green colors are unchanged. Rebased onto live 2.87.25 (`cd69f1d`).

Continuous top-25 IC idle ingest

Michele loop: periodically fetch ~25 most-used ICs → idle-process one-by-one into the **component library** → when empty, refetch, drop MPNs already present, top-up to **25 NEW**, repeat. Not a one-shot seed. Same exam pause as library scan.

Two libraries + writer gate + idle refresh

**Hard rule:** all chip-specific data lives in the **component library** (SoT). **Certification library** = standards/cert packs only. AF joins chip row + cert pack. Remote component-library writes restricted to `BOARDLAB_LIBRARY_WRITER_IDS`. Idle refresh pauses when any exam runs.

Deep rail power budget + library access

Deep per-rail **ordinary / peak** current budget (PE-BUD-001/002/003/010) with cited estimates — no silent skip. Library stores **power_requirements** (startup/ordinary/peak) and **parser_version**; **MySQL** is the management store (SQLite local fallback). Callers use **LibraryAccess** only. PCB PE-PWR/VIA prefer rail peak. Z inventory remains 2.87.22.

Inventory Z rewrite (AF-only + plane index)

**Michele product rule:** inventory Z computes only on **AF/SI protocol nets** plus nets the project **explicitly requests** (`ProjectFabSettings.impedance_nets`). Walking every routed non-POWER/GROUND net is enormous and useless — no silent full-board fallback. **Hot path rewrite:** `coverage_at` no longer rebuilds Shapely polygons per sample. Zone outlines become a per-board `_BoardPlaneIndex` (layer lists, prepared geometries, STRtree) once; samples only query. `exclude_net` (CPWG) filters the index without re-parsing outlines. Complexity drops from roughly \(O(S \cdot Z_\ell \cdot P)\) polygon rebuilds to \(O(Z \cdot P)\) build + \(O(S \cdot Q)\) queries (\(Q \ll Z_\ell\) candidates from the tree). Mid-run SSE reports `Z i/N (%) net (samples)`.

Fix `.kicad_pro` open-file accept

Chromium `showOpenFilePicker` rejects extensions with `_` («Extension '.kicad_pro' contains invalid characters»). Create-project no longer puts `.kicad_pro` in the `accept` list — it opens an untyped picker and filters by filename, then still loads sch/PCB via the folder `startIn` step. Invalid-accept errors fall back to folder pick.

Create from `.kicad_pro` (sch + PCB)

Create-project now starts from the **`.kicad_pro`** file: after you pick it, BoardLab requests the containing folder (Chrome `startIn`) and loads companion `.kicad_sch` / `.kicad_pcb` (plus hierarchical sheets). Dropping a project folder still works. The raw browser `TypeMismatchError` («path … not an entry of requested type») stays humanized; directory walks only call `getFile` on `kind === "file"` entries. Multi-unit symbols that share one reference across hierarchical sheets (e.g. COM Express `J12` units on `com_express_7_interfaces` + `com_express_7_mgmt`) no longer fail upload with «Duplicate reference». True clashes (same ref, different symbol/footprint) still error with both sheet names and a rename hint.

Clear KiCad folder pick (path type)

Michele saw the browser File System Access error «The path supplied exists, but was not an entry of requested type.» when opening a project after the `.kicad_pro` file-guide highlight. That string is `TypeMismatchError` (file vs directory), not KiCad CLI. Create-project now maps it to a clear hint: select the **folder** that contains `.kicad_pro` (not the file alone, not only `.kicad_pcb`). Lone file drops and folder picks without a `.kicad_pro` get the same guidance.

RMII data−clock timing (not skew-as-hold)

LAN8720A Table 5-11 `tsu`/`tihold` are TXD/TXEN setup/hold **to/after rising CLKIN** at the PHY pin. PE-AF-003 no longer treats inter-line skew (`Lmax−Lmin`) as the hold/setup budget. PCB measurable is **data−clock Δt**; full PASS still needs cited MAC clock-to-out (otherwise not certified / INSUFFICIENT). `toval`/`tohold` are PHY output characteristics — INFO cite only, not PCB flight PASS/FAIL. Inter-line skew is INFO FACT when measurable; Table 5-11 has no skew limit. REF_CLK 50 MHz (Table 5-12) unchanged.

Highlight `.kicad_pro` in downloads

On the File Upload Guide download / example list, the KiCad **`.kicad_pro`** project file is the primary callout — not buried among `.kicad_pcb`, sheets, or zip companions. Zip archives should contain / start from the `.kicad_pro`. Create-project upload UI unchanged.

100 MB project uploads

KiCad archives, PCB, stackup/fab docs, and datasheet PDFs may be up to **100 MB** (was 30 MB). The exact client message was `File too large (max 30 MB)` from the project upload router.

English UI menus

Chrome and project settings labels are English everywhere. No change to finding report content.

Analytic tpd from stackup ε_r

When fab `tpd_ps_per_mm` is empty but stackup/project cites ε_r (and W/H/T for outer microstrip), length→delay derives tpd analytically — **IPC-2141/Wheeler** microstrip ε_eff, stripline ε_eff=ε_r, `tpd=√ε_eff/c` with `c=0.299792 mm/ps`. Provenance **DERIVED** with formula + inputs. Manual/fab tpd still overrides. Missing geometry → clear FAIL (no invented ε_r). Sanity WARNING outside ~5–7.5 ps/mm FR-4. UI shows calculated tpd when computed from ε_r. Not BEM/FEM.

Impostazioni progetto (barra interna)

Project settings live in a segmented bar **inside** `/project/:id` (below the TopBar): BOM · Impedenza · Rail · Domini · Stackup / fab · Derating · Progetto. TopBar no longer has a duplicate Settings tab — the gear sheet is **Appearance only**, with a link to Impostazioni progetto.

Project Stackup & fab settings (tpd)

Project **Impostazioni stackup / fab**: cited tpd (ps/mm, with ps/inch helper), optional εr / note / fab PDF·MD. Empty = unknown — **no** silent 150 ps/in. Curated **JLCPCB** / **PCBWay** import profiles (VENDOR cite; tpd only when the maker page states it). RMII LAN8720A setup/hold uses project tpd for mm×tpd→ns (IMPLEMENTATION/FAB); missing tpd Action points at Stackup & fab settings.

RMII=PHY DS, MII=Clause 22, GMII=Clause 35

Michele model: RMII has no consortium/IEEE PCB cert — certify from the PHY datasheet in use (HubAudio → LAN8720A). MII from IEEE 802.3 Clause 22 (Section Two). GMII from Clause 35 (Section Three). AN-133 is optional helper only.

Schema USB Z N/A + ESD TVS + report default

HubAudio audit fix: Schema must not look like a failed PCB USB cert, and PESD TVS on USB_D± must suppress PE-ESD-001.

UI flow: no Docs limbo, login→dashboard, attach + severity colors

Exam flow: Schema vs PCB + status bar

Michele grey-zone fix: a schematic reprocess must never look like a fresh PCB report. Exam now has exactly two primary actions — **Analisi schema** and **Analisi PCB** — with separate reports and a bottom status bar (label + % + ETA) instead of the scrolling log wall. New projects auto-run **preparation** only (BOM / datasheets / graph), then wait for an explicit analysis choice.

Pair Zdiff calc + LAN8720A timing (HubAudio 46 Ω)

**FATTO for Michele.** HubAudio Ethernet **46.0053 Ω** was **single-ended Z0** (`w=0.2`/`h=0.1`), not Zdiff — ImpedanceFinder did not pair `RJ45_RXP`/`RXN`. Now: pair → always **differential Z** via IPC-2141A `coupled_diff_z` (=2·Zodd); SE → Z0 only; report `zdiff_*` vs `z0_*` split; actionable Action cites the target. Pack **LAN8720A** Table 5-11 timing (`lan8720a-rmii`) and emit **both** bus + PHY PE-AF-003 lines when both apply. Builds on 2.87.6 USB ±15% Zdiff work.

USB Zdiff ±15% tolerance (88≠ERROR)

USB D+/D− compare **Zdiff** to packed 90 Ω ±15% (USB 2.0 §7.1.1.1/§7.1.1.3 cable Z0; PCB `should` RECOMMENDED). Inside band → PASS; outside → WARNING; uncalculable → ERROR. Never SE Z0. Bus cite + datasheet VENDOR are two cert lines. IEEE 802.3-2012 §25.4.9.2.2 Ethernet is nominal 100 Ω with **no** ± band — outside stays ERROR; MDI pairs also use Zdiff only.

UI reorder: one shell, one report tree, KiCad-only ingress

Full frontend cleanup after iPad top-bar landed beside leftover sidebar-era report chrome. Report shows **only** the findings tree (+ Save as Markdown). Project create/replace is **KiCad folder only** — no BOM csv/xlsx or PADS/EDIF entry UI. Soft-bump on the 2.87 line (FPGA 2.88.x stays separate). No deploy until Michele says so.

U18 PE-PLC-002 thermal vias cite gate

ADAU1467WBCPZ300R (U18) was ERROR for `9 thermal vias … (min_via_count 49)`. The `49` came from datasheet p.203 Figure 87 — an **example** 7×7 via grid (“shows 49 vias”), not a mandatory minimum. Same EP/ESD cite rule: ERROR only for a MANDATORY count with cite; figure/example counts are REVIEW + quote, or skip with no cite.

HubAudio AF verify + re-run cue

Live already carried the 2.87.2 PE-AF-002 cleanup, but HubAudio's last PCB exam was still stamped **2.87.0** — so Michele still saw duplicate RD/TD “speed not identified”, ETH_MDIO 100 Ω, Italian RMII/USB tr/f. Replay of the saved HubAudio design/layout graphs confirms the fix. Soft-bump so the report version moves; **re-run HubAudio PCB exam** on live.

HubAudio AF noise: MDIO≠MDI, RD≡RX, USB/RMII cert

HubAudio PE-AF-002 cleanup on live 2.87.x. Ethernet MDI aliases (`RD+/−` ≡ `RXP/RXN`, `TD+/−` ≡ `TXP/TXN`) are one cert per pair; LAN8720A supplies 10/100 when the magnetics-side nets lack the PHY MPN. `ETH_MDIO` / `MDC` are management — not IEEE 100BASE-TX 25.4.9. USB D+/D− leave the AF tr/f skip (protocol 90 Ω cert owns them). RMII stays on the AN-133 PE-AF-003 English line.

Remove coffee/email progress notice

Drop the running-pipeline “grab a coffee / we’ll email you” banner. Progress shows a neutral “Pipeline running…” status instead.

Live integrate: iPad top-bar, MAC–PHY pack, USB/RMII cert

Combines the iPad top-bar shell (light default, Save as Markdown), the MAC–PHY bus catalog pack (Micrel AN-133, OPEN Alliance RGMII EPL V2.2, Cisco SGMII ENG-46158), USB 2.0 D+/D− cert lines versus the packed 90 Ω cite, RMII not-certified-on-recognition, and the `not_reviewed` count fix. One coherent live version above 2.86.0.

MAC–PHY bus pack (RMII/MII/RGMII/SGMII)

Packed Micrel AN-133, OPEN Alliance RGMII EPL V2.2, and Cisco SGMII ENG-46158 into the protocol catalog. Only explicitly stated NUMERIC fields with provenance. PCB Z0 / length stay UNKNOWN where the PDF does not state them. PE-AF-003 no longer certifies on recognition alone. HubAudio-style RMII (LAN8720A ETH_RXD/TXD/TXEN) reports `RMII not certified — because …` with the AN-133 cite when PCB impedance is UNKNOWN. SGMII uses the Cisco 100 Ω Rload / Rin 80–120 Ω cite when geometry allows a pair Z. RJ45/MDI 100 Ω stays separate.

USB / RMII cert lines; not_reviewed count

USB 2.0 D+/D− is one line: calculated pair Z versus the packed 90 Ω board cite. Certified names the measured ohm and the cite. Not certified says why — Z is outside that cite, or Z cannot be calculated from the PCB stackup/geometry. Missing length, stub, via, termination, rise/fall, and channel fields do not each warn. L3 is omitted when no channel fact is on file. LAN8720A ETH_RXD / ETH_TXD / ETH_TXEN are RMII (single-ended PHY–MAC), not RJ45/MDI 100 Ω. Recognition alone is not certification (fixed in 2.86.0). RJ45 pairs keep `Ethernet certified / not certified`. `not_reviewed` count matches the list (one designator per row). Real PCB AI failures go to `review_errors` with the exception message — not a blanket `pcb_review error` on every skip. ICs already in coverage are not listed as not-reviewed.

Exposed-pad names, ESD cites, CC-via-net, Ethernet pair Z

PE-BOM-011 treats EP, EPAD, THERMAL PAD, exposed pad, and the footprint's exposed land (including pin_count+1) as the same pad when both sides have one. A datasheet exposed pad with no land on the footprint stays ERROR. PE-ESD-001 says "datasheet-specified" only with a part and section/page. A 3V3 jack rail and VBUS are not warned without that cite. Optical S/PDIF (TOSLINK/optocoupler) is not an ESD warning; an unverified S/PDIF path stays a visible warning. PE-PRT-L0-001 follows Type-C CC pins (A5/B5) to the net and looks for the packed CabCon Rd 5.1 kΩ. The net does not have to be named CC1/CC2. PE-AF-002 on an Ethernet MDI pair compares one calculated pair Z to the packed cite for the speed on the board (LAN8720A 10/100 → 100 Ω, IEEE 100BASE-TX 25.4.9; Clause 40 only if gigabit). Inside is PASS, outside is FAIL, and no calculation is ERROR. No tr/f request.

Apple-like shell; USB-C vSafe still UNKNOWN

Shell Finder/Settings: sidebar, large title, system font, hairline. Findings tree keeps Error / Warning / Info folders (FAIL first) with + disclosure, then domains/rules, then Certificazioni/Protocolli. HDMI 1.4 TMDS electrical displays UNKNOWN — no guessed Zdiff. Alta Frequenza zip and `af-allegati` were searched for vSafe5V / vSafe0V. Contents are TI SI (`snla027b` AN-807, `sdaa499` EMI) — they do not state vSafe voltages. USB Type-C CabCon R2.5 §1.6 p.35 points at USB PD without a volt range. Charger Figure 4-39 4.75–5.5 V stays not-vSafe.

HDMI 2.0+ TI fields use source_type VENDOR

Michele exception: HDMI 2.0 and FRL electrical/PCB numbers from TMDS1204 / SLLA633 use `source_type=VENDOR` (not HDMI Forum STANDARD). TMDS1204-specific limits (skew, vias, FRL data_rate, SIGDET) are PHY_DEPENDENT with a document/rev/section cite and no number. HDMI 1.4 TMDS stays UNKNOWN. pcbsync.com not packed.

Protocol PDF archive + HDMI 2.0/FRL TI VENDOR overlay

On-disk archive `standards/protocol-specs/` (PDFs gitignored). INDEX.md lists cites. HDMI 2.0 and FRL take TMDS1204 Table 8-6 layout as VENDOR/PHY RECOMMENDED — not HDMI Forum STANDARD. HDMI 1.4 TMDS Zdiff stays UNKNOWN. pcbsync.com not packed.

TI TMDS1204 HDMI layout as VENDOR/PHY only

TMDS1204 datasheet SLLSF57A fills sink/source PCB layout (ZPCB 90 Ω / 75 Ω ranges, skew, length, vias, XTALK −24 dB, 5W spacing, RINT, AC cap) on physical ids `tmds1204-hdmi-sink` / `tmds1204-hdmi-source`. source_type PHY, source_class VENDOR, RECOMMENDED. Generic `hdmi-*` TMDS/FRL Zdiff stays UNKNOWN. SLLA633 is SIGDET wakeup (PHY_DEPENDENT), no layout ohms. pcbsync.com blog not packed.

HDMI CEC electrical from HDMI Specification 1.3

`CEC_HDMI_Specification.pdf` is High-Definition Multimedia Interface Specification Version 1.3 (22 June 2006), not a CEC-only pamphlet. CEC pull-up 27 kΩ, VOL 0.6 V, VOH 2.5 V, device 200 pF / cable 700 pF, interconnect 5 Ω are packed. TMDS/FRL Zdiff/skew stay UNKNOWN (Adopter spec still required). DDC/HPD not packed.

1000BASE-T from IEEE 802.3-2012 Section Three

IEEE Std 802.3-2012 Section Three Clause 40 fills 1000BASE-T: 1000 Mb/s, 100 m Class D link, cable 100 Ω, MDI return loss 16 dB (1–40 MHz), pair skew 50 ns, isolation 2 MΩ / 1500 V rms, MDI peak 0.67 V, link delay 570 ns. Cable 100 Ω is **CABLE**; L2 PCB Zdiff stays UNKNOWN. Clause 36 fills 1000BASE-X 1000 Mb/s (optical Zdiff N/A). Insertion-loss formula not packed as a single dB.

10BASE-T from IEEE 802.3-2015 Section One

IEEE Std 802.3-2015 Section One Clause 14 fills 10BASE-T: 10 Mb/s, 100 m design-objective link, cable 100 Ω ± 15 Ω, 11.5 dB link insertion loss, MAU TD return loss 15 dB, isolation 2 MΩ / 1500 V rms, TD peak 2.2 V. Cable 100 Ω is **CABLE**, not L2 PCB Zdiff. 1000BASE-T (Clause 40) is not in this volume.

Type-C CabCon R2.0 hole-fill (CC shall-detect; VBUS from R2.5)

USB Type-C Cable and Connector Specification Release 2.0 (August 2019) fills Source CC shall-detect voltages that R2.5 only illustrates as variance examples (Table 4-32 p.240: vRd 1.50 V, vOPEN 1.65 V, vRa 0.15 V). Type-C Current charger VBUS 4.75–5.5 V no-load / 4.0–5.5 V at 3 A, zOPEN 126 kΩ, tCCDebounce 100–200 ms, and tVBUSON 275 ms stay on newer CabCon R2.5 (Figure 4-39 / Tables 4-30, 4-32, 4-34). Rp/Rd/Ra unchanged. vSafe5V volt range still needs USB PD.

Protocol packs from USB 2.0 Rev 2.0 and Type-C CabCon R2.5

USB 2.0 Base Specification (April 27, 2000) fills LS 1.50 Mb/s, FS 12 Mb/s, HS 480 Mb/s, pull-up/down, VBUS 4.75–5.25 V, LS/FS edges. Cable Z0 90 Ω is `source_type=CABLE`; HS PCB traces *should* 90 Ω is RECOMMENDED PCB — L2 `differential_impedance` stays UNKNOWN so 45/50 Ω fixtures are not treated as Zdiff. Type-C Cable and Connector Specification Release 2.5 fills Rp/Rd/Ra from Tables 4-27/4-28/4-29. VBUS volts still need USB PD vSafe5V. IEEE 802.3 Section One/Three and HDMI Adopter remain missing.

Protocol packs from recovered PDFs (USB CTS, Type-C FTS, DVI 1.0, IEEE 802.3-2012 §2)

NUMERIC constraints now carry title, revision, section/table, and page from the recovered PDFs. USB 2.0 HS fills data rate / rise-fall / 1.5 kΩ pull-up / DCR from Electrical CTS v1.08; Zdiff stays UNKNOWN (CTS does not state 90 Ω). Type-C Rp/Rd/VBUS volts stay UNKNOWN (Functional Test Spec points at Cable and Connector tables). DVI 1.0 is a separate protocol from HDMI. IEEE 802.3-2012 Section Two fills 100BASE-TX cabling 100 Ω / 100 m / isolation and 100 Mb/s; 10BASE-T Clause 14 and 1000BASE-T Clause 40 are not in Section Two.

Protocol certification M6/M7 (USB-C / Ethernet / HDMI packs)

USB 2.0 (LS/FS/HS) is the protocol; USB Type-C is a connector/interface system; USB 2.0 over Type-C is the physical implementation. Type-C does not imply USB3 or USB4. Mini HDMI is a connector, not a protocol. Ethernet variants (10/100/1000/2.5G/5G/10G, SGMII, 1000BASE-X, 100BASE-FX, 10GBASE-R) are incomplete skeletons. All listed numeric fields stay **UNKNOWN** with `needed_document` (USB-IF / IEEE 802.3 / HDMI Adopter). No invented ohms, no typical-as-standard, no OpenEMS.

Protocol certification M10 (catalog skeletons)

Catalog skeletons and `required_checks` for **PCIe / CXL** (logical vs physical), **I2C**, **CAN**, **RGMII**, plus missing high-speed processor ids (PCI, PCI-X, CCIX, OpenCAPI, UPI, DMI, Infinity Fabric, HyperTransport, UCIe). Numbers stay **UNKNOWN / MISSING_SOURCE / PHY_DEPENDENT** until an official cite is in the pack. `pcb_relevant` is YES or CONDITIONAL as appropriate. No invented ohms, no USB-IF fill, no OpenEMS.

Protocol certification M9 (L3 channel + visible skip)

L3 **CHANNEL** certifier: structure for timing budget (TOTAL−USED=MARGIN), insertion loss, return loss, crosstalk, and complete channel. Numerical PASS/FAIL only when **existing channel FACT** (dB/ps) is already present — never invented S-parameters, never OpenEMS/FEM. Otherwise a visible skip: «Interfaccia X non certificata a L3 per mancanza di …». Internals (AXI/HBM) stay NOT_APPLICABLE. L0/L1 are not electrical. No M6 numeric packs.

Protocol certification M8 (DDR instance + L1 grouping)

DDR **physical instances** are controller-aware: one instance per memory device, DQ/DQS **byte lanes** separate from ADDRESS / COMMAND / CONTROL / CLOCK. Skew/length stay **CONTROLLER_DEPENDENT / PHY_DEPENDENT / UNKNOWN** — no universal mm/ps/ohm. HBM is package/interposer (`pcb_relevant: NO`); classic DDR PCB DQ rules are not applied. M6 numeric packs and L3 solver are not in this release.

Protocol certification M5 (Protocolli report)

Report section **Protocolli**: recognised instances, max level L0–L3 (L3 is a visible not-run skip, no solver), each check with measured / limit / margin / source / method, traceability chain net → group → physical interface → protocol → constraint → document → section. FAIL is listed first and styled as Error — not hidden under Warning (HubAudio). Visible skips stay on the page. No pack numbers, no invented Z, no OpenEMS.

Protocol certification M4 (L2 electrical)

L2 ELECTRICAL certifier: impedance, termination, voltage/levels, rise/fall when sources exist. Z only from datasheet / stackup / fabricator / **cited pack** — never invented 90 Ω USB. USB-IF/IEEE only if the pack has a cite. Silicon cross is max PCB × PHY subset when datasheet windows exist. Length is not delay. No L3/OpenEMS. L0/L1 are **not** electrical. RECOMMENDED never FAIL. MISSING_SOURCE / UNKNOWN when cite is absent. Visible skip when Z cannot be obtained.

Protocol certification M3 (L1 geometric)

L1 GEOMETRIC certifier: length, topology, vias, stubs, layer, grouping. Geometric skew only vs **NUMERIC** millimetre or an explicit **DESIGN LIMIT**. Otherwise UNKNOWN / VENDOR_DEPENDENT / CONTROLLER_DEPENDENT / PHY_DEPENDENT — never invent mm/ps. L1 is **not** electrical. No L2/L3. RECOMMENDED never FAIL. Internal interfaces stay NOT_APPLICABLE. Missing DQ/DQS grouping is a visible skip, not PASS.

Protocol certification M2 (L0 structural)

L0 STRUCTURAL certifier: nets must exist and connect at least two components. FAIL only for missing **MANDATORY** structure. AXI4 / internal interconnects are **NOT_APPLICABLE** (not FAIL). RECOMMENDED never FAIL. No L1–L3, no invented ohms/mm/ps.

Protocol certification M1 (instance recognition)

`physical_bus_instance` from declaration / silicon / part / pin / net / pairs. Output: instances, signal groups (DIFF pair, byte lane, clock/address), confidence. Ambiguity is **REVIEW**, never FAIL. AXI4 internal is recognised with `pcb_relevant: NO` and **no PCB nets**. No L0–L3 certifier. No invented ohms.

Protocol certification M0 (catalog, no numbers)

Versioned JSON protocol pack + Python loader/validator. Catalog skeletons for USB2 / USB-C-USB2 / 100BASE-TX / HDMI (connector distinct) / DDR / LPDDR / HBM / HyperBus / QSPI-octal / eMMC / UFS / AMBA / Wishbone / Avalon / TileLink / PCIe-CXL. Constraints without an official cite are UNKNOWN / CONTROLLER_DEPENDENT / PHY_DEPENDENT / MISSING_SOURCE — **no invented 90/100/50 Ω**. `logical_protocol_id` ≠ `physical_interface_id`. `pcb_relevant` is YES|NO|CONDITIONAL. RECOMMENDED is not FAIL-mandatory. Typical-as-standard is rejected by the parser. Report section **Protocolli** is empty (`nessun protocollo riconosciuto`). Recognition and L0–L3 certifiers are not in this release.

AF trace analysis (trigger, cascade, visible skips)

PCB exam adds **AF trace analysis** after unchanged `run_pcb_checks` (SI/HF stay). Trigger is λ/10 or tr/(6 tpd) from FACT only. Differential pairs are one unit. Z0/Zdiff only vs a **datasheet** window. Missing tr/f/εr/stackup/Z target/via span is a visible INSUFFICIENT finding («Pista ad alta frequenza non controllata per mancanza di …»), not invented 50/90 Ω. Trigger false → no AF finding. Numerical cascade is lossless RLGC sections (ImpedenceFinder Z0); not OpenEMS/FEM. Python. PE-AF-001 AI path unchanged.

Report Error group, J2, U18 max severity

The findings tree always has an **Error** folder when ERROR findings are visible. Group badge is the worst child (U18 PE-PLC-002 ERROR is not labeled WARNING). Connectors (J2) sit in the same sidebar as U*. PE-PLC stays in the PCB exam bucket. No auth change.

Module die, truncated QFN pintable, QFN=VQFN

HubAudio software leftovers on PE-BOM-010/011: a WROOM module is not the ESP32 die pintable; a QFN-48 land is not wrong because extraction stopped at pins 1–24; VQFN-24 4×4 is the same QFN family as datasheet QFN-24. Extra signal pads above the declared QFN-n still ERROR. Pad ≠ via. Kelvin unchanged.

PE-BOM-011 joins pins by name, not pin_count

Datasheet `pin_count` and PCB pad cardinality are incommensurable (USB-C 16P vs SH/mount/EP). PE-BOM-011 joins the pintable × KiCad `.kicad_mod` × embedded PCB pads by **pin name**. USB-C A5/B5 are CC pins, not EP. Missing pintable is a skip, never ERROR on `pin_count=16`. The library footprint is checked against the datasheet; lib vs embedded PCB is a separate mismatch. AI still extracts the table and runs review/class/SI — it does not count pads. Pad ≠ via.

Library component from PDF; AF+AI beside PCB checks

Library import registers a **component** (not only a PDF blob) with no exam. AF Board+AI is a pipeline section **after** unchanged `run_pcb_checks` (PE-SI / HF line stay in 2.62.1).

Library as its own product door

Standalone `/library` + `/api/library`: browse, add a datasheet PDF without an exam, update a component card. Datasheet prelim stays on the analysis path. Tests grouped datasheet → library → schematic → PCB → AF+AI (extra HF flags, then deterministic investigate). Rust criteria documented; no rustup. FEM out. DRC remains KiCad.

PCB analysis remainder (Phase B)

Stackup vs fab spec, via current with datasheet I (no IPC via chart), ESD pad distance TVS–connector, USB-PD contract, PoE isolation voltage, antenna keepout/matching, PDN Z(f). Same pipeline and finding quality as 2.61.2 / 2.62.0. Skip if no evidence. Not DRC. Not FEM.

HF lines/buses in PCB checks (Phase A)

USB / Eth / DDR / MIPI / PCIe / HDMI / LVDS / HF clock in `run_pcb_checks` at the same finding quality as 2.61.2. Pair integrity: stub (track only; via ≠ pad ≠ zone), reference-split under the line, BOM termination. CPU data/address/control and FPGA only if that device is on the graph. Skip if no evidence. Not DRC. Not FEM. Datasheet millimetres only; no invented Z/I.

Certifiers only for connectors on this board

USB-C / RJ45 / PoE / DDR3 are the method, not a catalog. If this graph has a USB-C receptacle, run USB-C questions. If it has RJ45, run Ethernet. PoE only with PoE evidence — never because RJ45 exists. No connector → no that certifier (not N/A). HubAudio has USB-C USB2 + PoE 10/100 MagJack and no DDR: no DDR findings. Skip-I (2.61.1) unchanged. No FEM, no via IPC, no invented I/Z/PoE/SuperSpeed.

Skip trace-width vs current without datasheet I

PE-PWR-001 (and PE-VIA-001) run only when the datasheet reports I_load / Imax / I_abs. Missing that number is a skip — not INFO INSUFFICIENT, not a typical USB 500 mA, not Iout_max-as-load. USB-C / Ethernet / PoE class certifiers still have no current/ampacity check. No via IPC table. No FEM.

Interface class certifiers (USB-C, Ethernet, PoE)

Dedicated per-interface certifiers (deterministic + AI explanation). Not generic SI. USB-C: CC1/CC2, Rp/Rd 5.1 kΩ, VBUS/GND, SuperSpeed only if the class is USB3. Ethernet: 10/100 vs GbE; magnetics required for GbE. PoE only with PoE evidence — a bare RJ45 is N/A, never invented PoE. Missing generation/class/ohms → INSUFFICIENT. DDR3 and via IPC ampacity are out of this slice. No FEM.

PCB software false positives

KiCad 9/10 boards have no numeric net table (`(net "GND")` on pads/tracks). The net index is filled from those names. PE-LAY-004 counts copper on **tracks, vias, and pours**, skips `unconnected-(…)` NC nets, and matches `/sheet/` prefixes — it must not report ~139 “unrouted” nets when KiCad DRC `unconnected_items` is ~30 (islands on already-named nets). Missing `I_load` is INSUFFICIENT on PE-PWR-001 / PE-VIA-001. Thermal/EP extra pads are not PE-BOM-011 ERROR. Voltage abs-max binds to the named pin. Kelvin ignores CRS/IN±. EMI/PI skip NC nets. LQW18AN `murata_lqw_inductance` decodes nH. FB/BLM beads are ferrite; DCR is not Z. Thinking `reasoning_content` echo unchanged.

Hierarchical sheets + DeepSeek thinking echo

Apri progetto still skips `.history` / `.git` / backups so the folder pick does not hang. It now keeps **every** linked schematic: all `*.kicad_sch` next to the `.kicad_pro`, plus `Sheetfile` / `(sheet` / `file=` children in a subfolder. Not only `HubAudio.kicad_sch`. DeepSeek thinking-only review turns (HubAudio U11/U12/U38) 400'd because the next request dropped `reasoning_content`. The native client echoes it on the follow-up. Retry failed IC reviews after this deploy.

Apri progetto does not walk forever

After folder permission, 2.60.8 kept `Next` disabled because `showDirectoryPicker` then recursed `dirHandle.entries()` / `getFile()` through the whole tree (HubAudio `.history` is ~2000 files). We only read the project directory: `.kicad_pro`, `.kicad_sch`, `.kicad_pcb`. Timeout shows an error instead of a spinner forever. Next enables when a `.kicad_pro` is in.

Folder picker, not Carica file dialog

Apri progetto opened the Mac file list (**Carica**, no row selected) because the control was a React `<input type="file" accept="">` without a working `webkitdirectory`. Empty Carica then looked like “no .kicad_pro”. It now uses `showDirectoryPicker` (Chrome) or a hidden input created with `webkitdirectory=true` and **no accept**. Cancel/empty pick is ignored.

Detect HubAudio.kicad_pro after folder pick

Apri progetto was rejecting the folder that actually contains `HubAudio.kicad_pro`. Safari/macOS folder pick often puts the real name in `webkitRelativePath` while `File.name` is the stem without `.kicad_pro`, and React was not setting `webkitdirectory` on the input. We match name **or** relative path, sniff JSON if the suffix is missing, and set the folder attribute on the DOM.

Apri progetto KiCad (cartella)

Un controllo: **Apri progetto KiCad**. Si sceglie la cartella dove sta il `.kicad_pro`. Carichiamo root + fogli hierarchical `.kicad_sch` e il `.kicad_pcb` fratello. Niente netlist, niente CSV. MPN solo da proprietà schematico (PNM/MPN/Value). Uno `.asc` PADS vecchio nella stessa cartella è ignorato.

Hierarchical schematic MPN when BOM omits a ref

graph_build reads `PNM` on `.kicad_sch` symbols (all nested sheets). If the CSV has no row for a designator, the child-sheet `PNM`/`MPN`/IC `Value` still fills `mpn`. Empty child-sheet fields stay empty — no invented part numbers. A sibling `.kicad_sch` next to a PADS netlist is consulted the same way.

KiCad PNM and honest missing-MPN skips

KiCad BOM column `PNM` is an MPN alias. Grouped `Reference` lists still split. IC `Value` fills MPN when PNM is blank (PCA9534ARGTR). Netlist-only U* with no BOM row are `INSUFFICIENT_EVIDENCE` (quoted Value/Footprint), not a silent drop and not an invented part number.

Ferrite Z from library MPN datasheet

graph_build looks up the bead MPN PDF in project `uploads/datasheets` and `library/datasheets` (named files and blob refs). Z is filled only when the PDF states impedance (e.g. 120 Ω @ 100 MHz). Missing Z stays omitted; graph_build does not abort.

Ferrite Z from datasheet, no graph_build abort

Beads with an MPN pull `impedance_ohm` from the datasheet or a quoted `N ohm @ freq` string. Missing Z after that is INSUFFICIENT, not a crash. Ohms are never written to `value_henries`.

Ferrite bead without Z still loads

Ferrite beads that only have current/DCR validate. Missing `impedance_ohm` is not invented and does not crash `graph_build`. Other inductors still need `value_henries`.

Incomplete PCB exam and owner project delete

Unfinished placing/routing still uses MODE=pcb. Parser and checks run on partial layouts; missing copper is INSUFFICIENT or skip, never invented millimetres. Via≠Pad unchanged. Dashboard owners can delete a project after a confirm dialog.

Analysis pipeline: project owner + LCSC lookup

BoardLab mark

New BoardLab mark (boardlab/lens) at the existing favicon and PWA pixel sizes.

PCB not_reviewed is board ICs, not the shared library

Emmaforo showed 20 “components not reviewed” that were other projects’ 1.5–1.7 extracts (LAN8720A, W25Q, …). BOM ICs were already 1.13.0 and *were* reviewed.

SI bus gate (EN RC ≠ USB series R)

Datasheet SI facts apply only to the bus in the quote. ESP32 EN RC 10 kΩ / 1 µF is not a USB D+/D− series resistor. USB without a library Z number stays measurement-only (88 Ω), not a 90 Ω FAIL. Coverage: PHY+RJ45 MDI, MAC–PHY RGMII/SGMII, DDR3, USB-C SuperSpeed.

BOM↔PCB↔datasheet, SPOF, EMI FACT, gated Tj

Remaining Fase B slices except auto-place and thermal FEM / OpenEMS.

ImpedenceFinder SI checks (not a dump table)

USB/HDMI/PCIe/ETH/LVDS/DDR layout_rules (diff/SE Z, skew, max length, spacing, ref plane, vias, layer, return, series R) are compared to ImpedenceFinder + copper. One PASS/FAIL/MARGIN finding per requirement. I2C/GPIO/CC/REGN are not 50 Ω.

PCB complete UI, not a raw SSE error

A finished PCB exam no longer shows the raw watcher string `pcb_status=complete (terminal)`. The SSE hatch emits `pcb_complete`; the PCB page then opens `/report?domain=layout` (expand-on-click tree).

ESD/PI filters, ERROR-first sort, findings tree

PE-ESD-001 only on J* ∩ IC nets (no NC / unconnected / VSYS/GND/3V3 spam). PE-PI-001 treats any capacitor on the rail, including KiCad `/` names, as decoupling. Report API and UI sort ERROR then WARNING then INFO, then RULE > RISK > REVIEW > INFO. The report left list is an expand-on-click tree (IC → pin/net → cards), not a dump of open groups.

Fase B: hierarchy, derating bands, timing, PI, ESD/return

Usable slices (not a platform): component→pin→net→block inventory, capacitor PASS/MARGIN/RISK from Vop/Vrated, RC/strap timing only with numbers, local vs bulk PI, ESD and HS return as REVIEW.

PCB Action on card + parsed geometry in AI context

Finding cards always show an **Action.** sentence (`action`, else `recommendation`, else a default). PCB AI context now includes vias under the footprint, copper thickness, nearby trace widths, courtyard, and keepout polygons from `.kicad_pcb`.

Finding engine (schema + PCB)

Same finding object on schematic analysis and PCB exam: FACT / REQUIREMENT / INFERENCE, datasheet provenance in the rule DB, RULE vs REVIEW, designer decisions, independent severity/confidence/evidence.

Shared library PCB exam (no second PDF pass)

Schematic and PCB share `library/extracted`. PCB AI consumes that cache (pintable required; no PDF attach). Report **PCB exam** section plus power-trace/thermal checks.

PCB review pipeline (exam, not auto-place)

Parallel `MODE=pcb` job examines an uploaded `.kicad_pcb`: domains/groups, trace inventory, deterministic layout checks, and per-IC AI datasheet review. Findings merge into the report with a Layout filter. No packing or pcbnew write-back.

Fix sign-in /login 404 after rebrand

Landing CTAs pointed at `/login`, which did not exist (page is `/sign-in`). Added redirects, accepted legacy JWT issuer `boardlab-local`, and CORS for both BoardLab and BoardLab hosts.

BoardLab name and finding IDs

Docker containers, deploy script and default site URL use the **BoardLab** name. Deterministic finding IDs use the `PE-*` prefix. Existing project files and browser storage keys are still read.

Antenna templates: IFA / meander / stub + .kicad_mod

Progetta antenna now returns a full parametric drawing: polyline segments (mm), SVG preview, and a downloadable KiCad footprint. Choose IFA, meander, or stub; geometry scales to the `antenna` zone when present. Still a routing template — no EM/VSWR invented.

RF / Impedance: verify antenna + design recipe

Project tab renamed **RF / Impedance**. Verify matching from IC ANT/RF pins toward an `ANT*` / `ANT_FEED` marker; Progetta returns microstrip `w` for 50 Ω (stackup or UI h/εr), optional λ/4 length from `f0`, and antenna-zone bbox. Auto-draw copper comes later — no EM/VSWR invented.

Classify strap/bootstrap satellites; hide other

Caps on EN/BOOT/REGN/PMID and bootstrap caps between IC pins get real roles. Unclassified `other` parts are dropped from satellites and assemble_order.

Cleaner Domains / Power rails membership

Power rails follow primary domain only. IC satellites for decoupling/bulk/filter/pullup stay on the IC’s primary supply rail (LDO 3V3 no longer inherits VSYS input caps). Connectors/switches drop out of noisy “other” satellites.

Stronger layout_rules extraction skill

Pintable skill now treats PCB / typical-application layout guidance as a first-class extract. Page trim keeps layout keywords; IC cache re-extracts once when `layout_rules` are empty under an older `model_version` (1.10.0+).

Placement F2 pack skeleton (gated)

Placement pipeline can propose satellite xy only when a `.kicad_pcb` layout exists and a `decoupling_proximity` rule has numeric `max_distance_mm`. No millimetres invented; otherwise `placement_pack.json` is skipped with an explicit reason.

Split Domains by primary supply rail

Domains no longer merge the whole board when a charger/LDO bridges VBUS→VSYS→3V3. Each IC is clustered by its primary supply rail (output for power ICs, regulated digital rail for consumers).

Domains & power-rail topology views

Browse routing-first functional groups from the project sidebar: Domains (power-net islands) and Power rails, each highlighting IC groups and satellite roles.

Unstick zombie running pipelines

A finished run whose worker died before flipping meta stayed `running`, so Progress showed Review spinning forever. Heal those projects when the event log already ends with `pipeline_complete`.

Stop progress→report bounce on finished projects

Opening a finished project no longer flashes Processing and dumps you on the report. Progress only auto-opens the report after a live run on that visit.

Fix project sidebar navigation

Opening a finished project no longer dumps you on the report with a stuck left menu. Hub first; Report stays in the sidebar. Leaving `/report` for BOM/tabs uses a full navigation so the page actually changes.

Placement pipeline (parallel)

Dedicated Placement job builds the routing-first topology plan without touching the analysis pipeline status or spending credits. No millimetres — domains, IC groups, satellites only.

Layout F1 topology + crystal/NC checks

Routing-first floorplan foundation without inventing millimetres: domains and satellite role hints after graph build, plus deterministic crystal CL and NC-pin checks.

DeepSeek roadmap integrations

Close the open P0/P2 items from the growth plan: offline smoke on the demo fixture, reviewer `shortest_path`, library promotion gate, PDF drop logging, per-stage cache hit-rate helper. IC placement stays Layout-product backlog.

Local multi-user auth

Self-host BoardLab accounts (email + password) so several people can share a project. Invite collaborators by email from the project page.

Prefer PCB nets for connectivity

When a `.kicad_pcb` is present, pad nets from the board drive the design graph. Schematic geometry alone was inventing swapped rails (GND↔3V3) and floating pins on good KiCad 10 designs.

KiCad power nets merge

`.kicad_sch` connectivity treated every `GND` power flag as its own island (`GND_`, `GND__`…), so the reviewer invented swapped rails and floating pins on good designs.

KiCad project zip upload

One zip (or every `.kicad_sch`) covers hierarchical sheets. If the zip has `bom.csv` and `.kicad_pcb`, those are taken too. Pipeline re-reads companions from storage.

Three file boxes

New project: BOM, schematic, and PCB on the first screen. PCB is optional.

Ask for the KiCad board

The create-project wizard has a dedicated PCB step (skip still allowed). Report load errors show the API detail instead of a generic fetch failure.

ImpedenceFinder Z0 on PCB nets

A pipeline run with `.kicad_pcb` + stackup samples routed **signal** nets (power/ground skipped). Extra net names can be analyzed from the Impedance tab. Z0 is ImpedenceFinder net_walk/zsolver; no invented εr.

Keepout courtyard

`layout_rules` `keepout` flags a foreign net whose track endpoint is inside the KiCad courtyard. Own net and missing courtyard skip. No invented analog/digital classes.

Crystal load caps and track path

Load caps on XIN/XOUT use the same `max_distance_mm` as decoupling. If the PCB has segments on the net, the limit is shortest-path length, not a guessed “loop is too big” ratio.

same_layer decoupling

If `layout_rules` sets `same_layer: true`, a decoupling cap on the opposite copper from the IC is a WARNING. A via inside the courtyard (calculated) is enough. Unset flag → skip.

Thermal vias vs min_via_count

Via count is calculated inside the KiCad courtyard. The limit is the `min_via_count` parameter from `layout_rules`. No courtyard or no count → skip. No pad radius default.

Layout SI skew (datasheet mm only)

Intra-pair skew is measured on the PCB only when `layout_rules` `length_match` has a number. 3W, creepage, and CPWG are not guessed.

Placement vs datasheet (PCB)

Decoupling distance is measured on the `.kicad_pcb` against `layout_rules`. No board → no `PE-PLC-001`. A null millimetre skips — no 3 mm default.

Finding review and ECO

Findings can be accepted, marked false-positive, or wontfix with a required reason. Accepted rows export as ECO; OpenEMS-style layout SI is still not this.

ImpedenceFinder calculator

The Impedance tab uses the closed-form engine from ImpedenceFinder (Hammerstad–Jensen / Cohn), not a second formula set and not OpenEMS.

Lifecycle and datasheet extras

Distributor lifecycle is a cached check, not a review scrape. Errata and layout_rules stay structured and skip when the catalog or the PDF has no number.

KiCad cad-bridge

BoardLab writes `boardlab-findings.json` next to the report so a KiCad 9/10 action plugin can pan to the symbol uuid on the right sheet.

Power margin, sequencing, DNP enable

Schema checks now compare regulator load to Iout_max, look at PG→EN when a sequence is declared, and treat DNP as a fitted-variant graph.

Filtri e termico schema

Deterministic checks now match RC/LC/π/T filters and estimate LDO/resistor dissipation without inventing missing numbers.

DC-bias C_eff stima

The derating table now shows an effective capacitance under DC bias for C0G/X7R/X5R ceramics. It is labelled *stima* — not a vendor lot curve.

Pull-up sizing and LDO Cout

Deterministic schema checks now size I2C pull-ups, flag NRST pull-downs, and look at LDO VOUT capacitance — still WARNING, never a invented datasheet µF ERROR.

DeepSeek V4.1 and re-analyze

BoardLab now defaults to DeepSeek-V4.1-Flash (`deepseek-flash`) for every LLM stage, shows API cost in dollars, and lets you replace the BOM and netlist on an existing project without deleting it.

Deeper datasheet review

Each IC review now sees more of the datasheet and starts from a structured abs-max table, so voltage, decoupling, and interface checks are less likely to stop at "Unverified".

Component library

Chips and passives stay in a shared library after the first look, so the next board does not re-download datasheets or re-extract pin tables.

Automatic datasheets

BoardLab now finds datasheet PDFs on its own. You can still upload a file, but you no longer need DigiKey keys for the common case.

DeepSeek API

BoardLab now talks to DeepSeek by default. Extraction skills run locally; datasheet PDFs are converted to text (and page images on the vision model) because DeepSeek does not accept native PDF documents.